1. Field of the Invention
The present invention is related to a semiconductor memory, and more particularly to a new configuration for redundant circuitry utilized in the burst mode in a 2-bit pre-fetch circuit or a multi-bit pre-fetch circuit of a synchronized dynamic random access memory (SDRAM).
2. Description of the Related Art
A synchronized DRAM (hereafter referred to simply as SDRAM) is a DRAM that performs internal operations in synch with a system-supplied clock, and is capable of faster operation than an ordinary DRAM. This SDRAM is also supplied with system-supplied command signals, which specify operating modes. By internally decoding these applied command signals, the SDRAM determines the system-requested operating mode, and, for example, outputs read data in accordance with a specified operating mode.
One of the above-mentioned operating modes is a burst mode. Increasing clock speeds have made it impossible for internal memory operations to be performed within a single clock cycle. This burst mode allows the simultaneous reading and writing of a plurality of addresses, and writes or outputs the memory data of sequential addresses that have an externally-supplied address as their starting address. Accordingly, the number of sequentially outputted bits are specified as 2-bit, 4-bit or 8-bit.
With such a burst mode, an SDRAM internally generates consecutive addresses based on an external address, and outputs memory data by decoding these addresses. With a 2-bit burst mode, a single internal address is generated. With a 4-bit burst mode, one internal address is generated, and during the next clock cycle, two internal addresses are generated. And with an 8-bit burst mode, one internal address is generated, and during the next three clock cycles, two internal addresses are generated per cycle.
Under these circumstances, the internal memory cell array of an SDRAM is divided into an odd address memory cell array and an even address memory cell array, and in the burst mode, an SDRAM supplies an externally-supplied or internally-generated address, whose least significant bit is removed, to the column decoders of the odd address memory cell array and the even address memory cell array. The use of such an architecture enables the sequential output of 2-bit memory data at all times. This architecture is called a 2-bit pre-fetch circuit. Similarly, a 4-bit pre-fetch circuit, which enables the simultaneous reading and writing of 4-bit memory data, is also possible. In this case, addresses whose least significant two bits are removed are supplied to the respective column decoders of four memory cell arrays.
FIG. 1 depicts an example of a 2-bit pre-fetch circuit in a conventional SDRAM. In this example, the memory cell array is divided into an odd address memory cell array 10 and an even address memory cell array 20. And for each memory cell array 10, 20, an address predecoder 11, 21 and address main decoder 12, 22 are provided. In addition, the output from each memory cell array 10, 20 is amplified by a data bus amp 13, 23.
SDRAM operates in synch with a system-supplied clock CLK. Therefore, according to the timing of a clock 31 outputted from a clock buffer 30, which captures the clock CLK, a command signal 2 (Comm) is latched to a command latch and decoder 32, and an address signal 3 (Add) (in this example, eight bits from a0 to a7) is latched to an address buffer 33. And then, an address signal a3-a7 from the address buffer 33 is latched to an address latch 38 based on the timing of an address latch clock 35 generated by the command latch and decoder 32. An address signal a1, a2 is also latched to an address latch and counter 39 based on the same clock 35.
An address signal a3-a7 is supplied as-is to odd and even address predecoders 11, 21. Meanwhile, an address a1, a2 is supplied as-is to the odd address predecoder 11. An address a1, a2 is also supplied to the even address predecoder in accordance with the value of the least significant address a0, that is, according to whether it is odd or even, either as-is as a latched address 44 or as a new shifted address 48, in which the address is incremented by 1 by an address arithmetic circuit 46.
Thus, when the external address is even, even memory data 24 amplified by an even data bus amp 23 is latched to an output data latch 16 based on clock 56 timing, and then odd memory data 14 amplified by an odd data bus amp 13 is latched to an output data latch 26 based on clock 57 timing, and even and odd data are sequentially outputted in that order through output terminal DOUT.
Further, when the external address is odd, odd memory data 14 is latched to the output data latch 16, and even memory data is latched to the output data latch 26, based on timing supplied by clocks 56, 57, respectively, and odd and even data are sequentially outputted in that order.
In line with increasing memory capacity, a redundant cell array is being added to a memory cell array to prevent a drop in memory yield. In line with adding such a redundant cell array, it is necessary to provide a redundant address read-only memory (ROM), which stores the address of a defective cell substituted for by a redundant cell array, and an EOR circuit, or a redundant address comparator, which determines whether or not this redundant address matches the address currently being accessed.
However, when a redundant cell array architecture is applied to memory in the above-described 2-bit pre-fetch circuit architecture, because there are an internal odd address cell array 10 and even address cell array 20, it is necessary to provide a redundant cell array, and both a redundant column address ROM and redundant address comparator for each cell array. Firstly, since this involves providing duplicate redundant column address ROM and redundant address comparators, the size of the circuit architecture increases. And secondly, when a redundant cell array is provided for both the odd and even cell arrays, when each has a redundant column address ROM, these redundant column address ROM cannot be used efficiently. That is, judging from the probability of a defective cell occurring, there is less probability of both the odd address cell array and the even address cell array using an entire redundant cell array. Therefore, there is an extremely low probability both redundant column address ROM for both cell arrays will utilize 100% of their capacity for storing redundant addresses. The above-mentioned problem is the same for a 4-bit pre-fetch architecture, and is generally also the same for multi-bit pre-fetch architectures.
Thus, an object of the present invention is to provide a semiconductor memory with an efficient architecture for the redundant circuitry of a redundant cell array for a multi-bit pre-fetch circuit architecture.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for a redundant ROM, which stores a redundant address of a redundant circuit of a redundant cell array for a 2-bit or larger multi-bit pre-fetch circuit architecture.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for redundant address wiring from a redundant column address ROM to a redundant address comparator.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for a redundant address comparator of a redundant circuit of a redundant cell array for a 2-bit or larger multi-bit pre-fetch circuit architecture.
Another object of the present invention is to provide a semiconductor memory with an efficient architecture for a redundant address comparator of a redundant circuit.
To achieve the above-stated objects in a memory, in which an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.
The present invention can be applied to a 4-bit or larger multi-bit pre-fetch circuit architecture. For example, a 4-bit pre-fetch architecture internally comprises a first address group memory cell array and redundant cell array, a second address group memory cell array and redundant cell array, a third address group memory cell array and redundant cell array, and a fourth address group memory cell array and redundant cell array. In this case, redundant memory stores redundant addresses for the first through the fourth address groups, together with selection data for the first through the fourth address groups. This holds the same for 8-bit and larger pre-fetch architectures as well. Therefore, the invention applies to a semiconductor memory, which, at a minimum, comprises at least a first address group and a second address group memory cell array and redundant cell array.
The above-mentioned first invention is a semiconductor memory, having a first address group cell array corresponding to a first address group, and a second address group cell array corresponding to a second address group, said semiconductor memory comprising: a first address group redundant cell array, which can be substituted for a defective cell of the above-mentioned first address group cell array; a second address group redundant cell array, which can be substituted for a defective cell of the above-mentioned second address group cell array; a redundant memory, which stores a first address group redundant address or a second address group redundant address corresponding to the above-mentioned defective cell, together with first and second address group selection data corresponding thereto; a first address group redundant address comparator, which compares a redundant address of the above-mentioned first address group supplied from the above-mentioned redundant memory with an address of a first address group to be accessed, and when they match, effectuates the selection of the above-mentioned first address group redundant cell array; and a second address group redundant address comparator, which compares a redundant address of the above-mentioned second address group supplied from the above-mentioned redundant memory with an address of a second address group to be accessed, and when they match, effectuates the selection of the above-mentioned second address group redundant cell array.
A second invention supplies an odd redundant address and even redundant address in a redundant memory in the first invention to an odd redundant address comparator and an even redundant address comparator via separate redundant address lines.
Furthermore, a third invention is a modification of the second invention, and supplies, on a time-sharing basis, an odd redundant address and even redundant address in a redundant memory in the first invention to an odd redundant address comparator and an even redundant address comparator via a common redundant address line. The above-described second and third present inventions can also be applied to 4-bit and larger multi-bit pre-fetch circuit architectures.
A fourth invention is a semiconductor memory with a 2-bit pre-fetch architecture, which comprises an odd address cell array and an even address cell array, this semiconductor memory providing each cell array with a redundant cell array, and comprising redundant address comparators corresponding to each redundant cell array, these comparators being comprised of a redundant address comparator for a common upper address, and an odd redundant address comparator and an even redundant address comparator for individual lower addresses. This simplifies a redundant address comparator. The present invention can also be applied to 4-bit and larger multi-bit pre-fetch circuit architectures.
The above-mentioned fourth invention is a semiconductor memory, having a first address group cell array corresponding to a first address group, and a second address group cell array corresponding to a second address group, said semiconductor memory comprising: a first address group redundant cell array, which can be substituted for a defective cell of the above-mentioned first address group cell array; a second address group redundant cell array, which can be substituted for a defective cell of the above-mentioned second address group cell array; a redundant memory, which stores a redundant address corresponding to the above-mentioned defective cell; a first address group lower redundant address comparator, which compares a lower address of the above-mention redundant address supplied from the above-mention redundant memory with a lower address of the first address group to be accessed; a second address group lower redundant address comparator, which compares a lower address of the above-mentioned redundant address supplied from the above-mentioned redundant memory with a lower address of the second address group to be accessed; and a common upper redundant address comparator, which compares an upper address of the above-mentioned redundant address supplied from the above-mentioned redundant memory with a common upper address of a first address group and second address group to be accessed.
In addition, when there are a plurality of redundant cell arrays, which relief defective cells in a cell array, regardless of whether it is odd or even, a fifth invention stores in redundant memory the redundant addresses of these defective cells, together with selection data for a plurality of redundant cell arrays, supplies, on a time-sharing basis, redundant addresses to redundant address comparators corresponding to a plurality of redundant cell arrays. As a result, it is possible to simplify the lines from redundant memory to redundant addresses.
The above-described fifth invention is a semiconductor memory, having a cell array, and a plurality of redundant cell arrays, which are capable of substituting for a defective cell in this cell array, said semiconductor memory comprising: a redundant memory, which stores a redundant address corresponding to the above-mentioned defective cell, together with selection data for the above-mention plurality of redundant cell arrays; wherein a redundant address comparator, which is provided for each of the above-mentioned redundant cell arrays, and which compares the above-mentioned redundant address supplied from the above-mentioned redundant memory with the address to be accessed, and when they match, effectuates the selection of the corresponding above-mentioned redundant cell array; wherein the above-mentioned redundant memory supplies to the above-mentioned plurality of redundant address comparators, on a time-sharing basis, the plurality of above-mentioned redundant addresses stored in accordance with the above-mentioned selection data.
Furthermore, in an N-bit pre-fetch architecture (where N=2m, and M is an integer of 1 or larger), there are number of both address groups and memory cell arrays.